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Sergi Alcaide
Also published under:S. Alcaide
Affiliation
Barcelona Supercomputing Center (BSC), Barcelona, Spain
Topic
Safety-critical,L2 Cache,Assignable Cause,Benchmark,Avionics,Instruction Set Architecture,Single Fault,Error Detection,Forward Error Correction,Multi-core,Open-source,Open-source Hardware,Commercial Off-the-shelf,Fault-tolerant,Graphics Processing Unit,Hardware Modules,Hardware Support,Operating System,Software Solutions,System-on-chip,Traffic Patterns,Verification And Validation,Voltage Sag,Benchmark Suite,Circuit Simulation,Core Processes,Corrective Actions,Data Cache,Electronic Design Automation,Error Handling,Export Restrictions,Hardware Cost,Hardware Modifications,Increase In Execution Time,Matrix Multiplication,Memory Control,Open-source Implementation,Remote Memory,Serialized,Software Testing,Space Domain,Vehicle Safety,3D Architecture,3D Integration,AI Models,Access Latency,Application Programming Interface,Automotive Systems,Autonomous Vehicles,Average Execution Time,
Biography
Sergi Alcaide is a PhD student at the Universitat Politècnica de Catalunya (UPC) and Barcelona Supercomputing Center. His research interests include computer architecture and reliability. He received a master in innovation and research in informatics at UPC. Contact him at [email protected].