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Victor Champac
Also published under:V. Champac, V. H. Champac
Affiliation
National Institute of Astrophysics, Optics and Electronics (INAOE), Puebla, Mexico
Topic
Defect Model,Gate Electrode,Metal Gate,NAND Gate,Analytical Form,Average Relative Error,Behavioral Defects,CMOS Technology,Cell Behavior,Channel Length,Compact Model,Continuous Scale,Cosmic Rays,Critical Path,Defect Size,Delay Increases,Depth Map,Double-gate,Dust Particles,Electron Density,Electron Hole Pairs,Electronic Components,Equivalent Resistance,Fault Location,Fault Simulation,Fin Height,FinFET Technology,Fluctuations In Parameters,Gate Oxide,Graphical Analysis,Incident Ions,Inductive Load,Input Vector,Inverter,Iterative Process,Layout Design,Linear Energy Transfer,Local Variations,Low Power Consumption,Manufacturing Process,Memory Cells,Network Strength,Normal Distribution,Open Location,Oxide Thickness,Oxygen Ions,Pair Of Vectors,Parallel Resistance,Particle Tracking,Possibility Of Occurrence,
Biography
Victor Champac has been with INAOE-Mexico since 1993, where he is Titular Professor. He was the co-founder of the TTTC-Latin America, and Co-General Chair of the 2nd and 9th IEEE LATW conference. He is member of the Board Director of JETTA. His research lines include the development of new test strategies, signal integrity, process variation, and noise tolerant VLSI Circuit Design.