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Victor Avendaño
Also published under:Victor Avendano, V. Avendano
Affiliation
Freescale Semiconductor, Guadalajara, Mexico
Topic
Clock Period,Combinational Logic,Critical Signaling,Increased Power Consumption,Input Signal,Integration Of Signals,Inverter Output,Logic Level,Power Consumption,Propagation Delay,Setup Time,Supply Voltage,Time Delay,Transistor Size,Area Overhead,Aspect Ratio,Channel Length,Channel Width,Circuit Applications,Circuit Simulation,Clock Signal,Coupling Coefficient,Delay Line,Design Methodology,Detection Probability,Detection Threshold,Digital Circuits,Digital Signal,Electric Simulation,Flip Flop,Flip-flop Design,Gate Oxide,Global Interconnectedness,High-performance System,High-speed Signal,Higher Frequency,Integrity Violations,Logic State,Low-level Signals,Magnitude Of Noise,Output Load,Performance Monitoring,Planning Phase,Process, Voltage And Temperature,Setup Delay,Single Monitoring,Speed Requirements,Stable State,Stable Values,Sufficiently Large,
Biography
Victor Avendaño was born in Veracruz, Mexico. He received the B.S. degree in electronic engineering from the Technological Institute of Veracruz, Veracruz,Mexico, in 1998, and the M.S. and Ph.D. degrees in electronic engineering in 2000 and 2005, respectively.
In 2005, he joined Freescale Semiconductor Mexico, Tlaquepaque, Mexico, where he is currently a senior integrated circuit (IC) design engineer of the Networking and Multimedia Group, and has been engaged in the design of IO and serializer/deserializer (SERDES) blocks.
In 2005, he joined Freescale Semiconductor Mexico, Tlaquepaque, Mexico, where he is currently a senior integrated circuit (IC) design engineer of the Networking and Multimedia Group, and has been engaged in the design of IO and serializer/deserializer (SERDES) blocks.