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Jong-Wan Jung
Affiliation
Massachusetts Institute of Technology, Cambridge, MA, USA
Topic
Gate Oxide,Sheet Resistance,2-step Method,Average Strain,Chemical Vapor Deposition,Compressive Strain,Computerized Image Analysis,DRAM Technology,Endpoint Detection,Etching,Etching Process,Gate Stack,Grating,Heat Budget,High-temperature Annealing,Inductively Coupled Plasma,Low-temperature Oxidation,Magnetic Field,Metal Etching,Oxide Interface,Perimeter,Plasma Etching,Plasma-induced Damage,RF Power,Rapid Thermal Annealing,Sensitive Measure,Silicide,Silicon-on-insulator,Steady State,Strain Measurements,Surface Plots,Thermal Oxidation,Transient Component,Two-step Annealing,Word Line,Active Layer,Doped Layer,Epitaxial Growth,Epitaxial Layer,GaAs Substrate,High Doping Concentration,Low Series Resistance,Metal Gate,Phase Noise,Series Resistance,Strip Width,
Biography
Jong-Wan Jung recieved the M.S. and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology, Korea, in 1991 and 1996, respectively.
From 1996 to 2001, he was a Senior Member of Technical Staff in the field of logic and DRAM device development, at Hynix Semiconductor, Inc., Korea. Since 2001, he has been working as a Postdoctoral Researcher at M.I.T., Cambridge, MA. His current research interests include nano-scale CMOS and SiGe/Si technology.
From 1996 to 2001, he was a Senior Member of Technical Staff in the field of logic and DRAM device development, at Hynix Semiconductor, Inc., Korea. Since 2001, he has been working as a Postdoctoral Researcher at M.I.T., Cambridge, MA. His current research interests include nano-scale CMOS and SiGe/Si technology.