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Jeff Gambino
Also published under:J. Gambino, J. P. Gambino, Jeffrey P. Gambino, Jeff P. Gambino, Jeffrey Gambino
Affiliation
Gresham, OR
Topic
Dielectric Relaxation,Metal Layer,Power Devices,Scanning Electron Microscopy,Activation Energy,Al Layer,Amorphous Layer,Amount Of Damage,Analog-to-digital Converter,Bond Wires,Capacity Density,Conventional Process,Corrosion Reaction,Current Flow,Depth Of Cut,Dielectric Constant,Dielectric Process,Edge Chipping,Electrode,Electron Emission,Energy Dispersive Spectroscopy Analysis,Energy-dispersive X-ray Spectroscopy,Experimental Design,Feed Rate,Final Test,High Dielectric Constant,High Voltage,Image Sensor,Initial Relaxation,Metal Layer Thickness,Metal-insulator-metal Capacitor,Metallic Structures,Negative Bias,Reactive Ion Etching,Reliability Of Power Devices,Reliable Evaluation,Scribe Line,Segmentation Process,Shear Strength,Single-photon Avalanche Diode,Smart Power,Space Applications,Spindle Speed,Thermal Oxidation,Tin Electrodes,Tin Oxide,Top Plate,Ultrasonic Power,Voltage Pulses,Yield Losses,
Biography
John Faltermeier received the B.S. degree in physics and the Ph.D. degree in physics from the University at Albany in 1992 and 1997, respectively.
He joined IBM's Advanced Semiconductor Technology Center, Hopewell Junction, NY, in 1997 and developed single wafer processes applied to advanced DRAM products. Concurrently, he worked on gate materials for Gb DRAM technology. In 1999, his responsibilities were shifted to contact level module coordination for 0.15 $\mu$ m and 0.135 $\mu$ m DRAM nodes. In 2000, he joined the Logic and Embedded DRAM alliance as STI module coordinator to develop isolation technologies for 0.18 and 0.14 $\mu$ m embedded DRAM products. He is currently an advisory engineer in IBM's Semiconductor Research and Development Center.
He joined IBM's Advanced Semiconductor Technology Center, Hopewell Junction, NY, in 1997 and developed single wafer processes applied to advanced DRAM products. Concurrently, he worked on gate materials for Gb DRAM technology. In 1999, his responsibilities were shifted to contact level module coordination for 0.15 $\mu$ m and 0.135 $\mu$ m DRAM nodes. In 2000, he joined the Logic and Embedded DRAM alliance as STI module coordinator to develop isolation technologies for 0.18 and 0.14 $\mu$ m embedded DRAM products. He is currently an advisory engineer in IBM's Semiconductor Research and Development Center.