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Fen Chen
Also published under:F. Chen
Affiliation
Apple Inc., Cupertino, CA, USA
IBM Microelectronics, Essex Junction, VT, USA
IBM Microelectronics, Essex Junction, VT, USA
Topic
Dielectric Breakdown,Gate Dielectric,Technology Node,Time-dependent Dielectric Breakdown,Voltage Drop,Acceleration Model,Acceleration Voltage,Big Data,Chemical Vapor Deposition,Compressive Stress,Defect Density,Low Voltage,Metal Lines,Power-law Model,Stress Field,Voltage Stress,3D Technology,Acceleration Factor,Accurate Determination,Activation Energy,Active Space,Actual Voltage,Analytical Methods,Area Ratio,Arrival Rate,Back-end-of-line,Big Data Analytics,Breakdown Mechanism,Change In Slope,Charge Transfer Reaction,Conduction Band,Conduction Mechanism,Correction Model,Current Stress,Data Analysis Methods,Data Generation,Data Generation Method,Deconvolution Of Data,Detailed Evolution,Diagnostic Methods,Diagnostic Reliability,Diagnostic Results,Diagnostic Studies,Dielectric Constant,Dielectric Spacer,Direct Tunneling,Distribution In Space,Drop In Resistance,Electrochemical Reaction,Electrode Kinetics,
Biography
Fen Chen received the Ph.D. degree in electrical engineering from the University of Delaware, Newark, DE, USA, in 1998.
He joined IBM Microelectronics, Essex Junction, VT, USA, in 1998. He joined the Reliability Engineering Group, Apple Inc., Cupertino, CA, USA, in 2015. He holds more than 40 patents and has authored over 50 technical papers.
Dr Chen was the Chairman of the JEDEC 14.2 Wafer Level Reliability Commitee (2013–2015).
He joined IBM Microelectronics, Essex Junction, VT, USA, in 1998. He joined the Reliability Engineering Group, Apple Inc., Cupertino, CA, USA, in 2015. He holds more than 40 patents and has authored over 50 technical papers.
Dr Chen was the Chairman of the JEDEC 14.2 Wafer Level Reliability Commitee (2013–2015).