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K. Ariyoshi
Also published under:Keiko Ariyoshi
Affiliation
AIST Tsukuba Central 2, National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki, Japan
Toshiba Corporation, Kawasaki, Kanagawa, Japan
Toshiba Corporation, Kawasaki, Kanagawa, Japan
Topic
Gate Oxide,Shielding Effect,Acceptor Concentration,Blocking Voltage,Bottom Region,Epitaxial Growth,Gate Stack,Bilayer Structure,Bulk Layer,Carrier Mobility,Chemical Vapor Deposition,Conventional Devices,Cross-sectional Transmission Electron Microscopy,Crystal Orientation,Dielectric Parameters,Dielectric Thickness,Doped Layer,Effective Penetration,Equivalent Oxide Thickness,Excellent Scalability,Fabrication Process,Field-effect Transistors,Gate Capacitance,Gate Electrode,Hexagonal Cell,High Electric Field,High Field,High Threshold Voltage,Interfacial Layer,Inversion Layer,Low Electric Field,Low On-resistance,Metal Gate,Metal Gate Stacks,Middle Point,Negative Gate Voltage,Nitride,Nitrogen Addition,Numerical Calculations,Parasitic Capacitance,Physical Thickness,Physical Vapor Deposition,Poisson Equation,Potential Barrier Height,Sheet Resistance,Sidewall,Silicon Carbide,Strong Inversion,Technology Node,Thin Layer,
Biography
Keiko Ariyoshi received the B.S. and M.S. degrees in crystalline materials science from Nagoya University, Nagoya, Japan, in 2003 and 2006, respectively.
She was with the Research and Development Center, Toshiba Corporation, Kawasaki, Japan, where she was engaged in the research on high-$k$ dielectrics for advanced Flash memories. In 2008, she was assigned to Toshiba America Electronic Components, Inc., Albany, NY, where she has been working on the research and development of high-$k$ and metal gate stacks for advanced CMOS devices.
She was with the Research and Development Center, Toshiba Corporation, Kawasaki, Japan, where she was engaged in the research on high-$k$ dielectrics for advanced Flash memories. In 2008, she was assigned to Toshiba America Electronic Components, Inc., Albany, NY, where she has been working on the research and development of high-$k$ and metal gate stacks for advanced CMOS devices.